The present invention relates to semiconductor device fabrication technology, and more particularly, to a method for fabricating a semiconductor device with a vertical channel transistor.
As the integration degree of a semiconductor device increases, a channel length of a transistor is gradually reduced, causing device characteristics to be deteriorated due to a short channel effect. To avoid the short channel effect, there have been proposed various methods of reducing a depth of a junction region or relatively increasing a channel length by recessing a channel region of a transistor.
However, there is an increasing demand for a smaller-sized transistor as the integration density of a semiconductor memory device such as a dynamic random access memory (DRAM) approaches gigabit scale. Recently, a transistor of a DRAM requires a device area of 4F2 (F: minimum feature size). Therefore, it is difficult to meet the requirement for a device area despite the scaling-down of a channel length in a typical planar transistor structure where a gate electrode is formed over a substrate and junction regions are formed at both sides of the gate electrode.